With significant progress in chip manufacturing technology, the complexity of available architectures is increasing with higher core count, depth of the memory hierarchy and greater heterogeneity with integrated GPUs, FPGAs or NICs. This diversity of designs to reach the exascale era leads to growing concerns regarding applicative performance. To squeeze the maximum level of performance out of these complex SoCs, runtime systems and performance modelling will play a major role to deal with the complexity of the underlying architecture. The objective of this workshop is to share latest updates on these topics. This includes, thread/task scheduling, benchmarking and tuning of applications and algorithms on emerging platforms.
Topics of interest
For this workshop we welcome original work, presenting state of practice and state of the art and covering different aspects of thread/task scheduling, GPU task engine, programming models from system to application level for parallel applications on complex SoCs. We will also welcome surveys, position papers or standardization proposal. The workshop will cover the following topics :
- Scheduling on complex SoCs
- Runtime systems
- Data-movement reduction (e.g compute near-data paradigm)
- Performance evaluation and prediction
- Real-world case studies
- Marc Perache, CEA
- Fabrice Dupros, Arm
- Balazs Gerofi, RIKEN
- Clay Hughes, Sandia National Lab.
- Emmanuel Jeannot, Inria
- Hatem Ltaief, KAUST
- Sameer Shende, U. of Oregon
- Philippe Thierry, Intel
How to submit
Submissions should be in PDF format , and should be formatted in a double-column format with a font size 10 pt or larger. They should not exceed 10 pages (all inclusive). All accepted papers will be published in the ACM Digital Library
- Please follow the ACM format : https://www.acm.org/publications/proceedings-template
- Submission Link : https://easychair.org/my/conference?conf=exa-pmra20
This half-day workshop will be held in conjunction with ICPP 2020 - The 49th ACM International Conference on Parallel Processing
- Paper Submission: May 10, 2020 (AoE)
- Author Notification: June 1, 2020
- Camera ready : June 15, 2020
- Workshop Dates: August 17, 2020
List of Accepted Papers (tentative)
- Fast Modeling of Network Contention in Batch Point-to-point Communications by Packet-level Simulation with Dynamic Time-stepping, Z.Hang et al.
- Exploiting Dynamism in HPC Applications to Optimize Energy-Efficiency, M.Kumaraswamy et al.
- Accelerating Forward-Backward Sweep Power Flow Computation on the GPU, S. Shah et al.
- Feature-preserving Lossy Compression for In Situ Data, I. Yakushin et al.