With significant progress in chip manufacturing technology, the complexity of available architectures is increasing with higher core count, depth of the memory hierarchy and greater heterogeneity with integrated GPUs, FPGAs or NICs. This diversity of designs to reach the exascale era leads to growing concerns regarding applicative performance. To squeeze the maximum level of performance out of these complex SoCs, runtime systems and performance modelling will play a major role to deal with the complexity of the underlying architecture. The objective of this workshop is to share latest updates on these topics. This includes, thread/task scheduling, benchmarking and tuning of applications and algorithms on emerging platforms.

Topics of interest

For this workshop we welcome original work, presenting state of practice and state of the art and covering different aspects of thread/task scheduling, GPU task engine, programming models from system to application level for parallel applications on complex SoCs. We will also welcome surveys, position papers or standardization proposal. The workshop will cover the following topics :

Program Chairs

Program Committee

How to submit

Submissions should be in PDF format , and should be formatted in a double-column format with a font size 10 pt or larger. They should not exceed 10 pages (all inclusive). All accepted papers will be published in the ACM Digital Library

Important dates

This half-day workshop will be held in conjunction with ICPP 2020 - The 49th ACM International Conference on Parallel Processing

List of Accepted Papers (tentative)